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DM74LS161A/DM74LS163A Synchronous 4-Bit Binary Counters
March 1998
DM74LS161A/DM74LS163A Synchronous 4-Bit Binary Counters
General Description
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The LS161A and LS163A are 4-bit binary counters. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable input. The clear function for the LS161A is asynchronous; and a low level at the clear input sets all four of the flip-flop outputs low, regardless of the levels of clock, load, or enable inputs. The clear function for the LS163A is synchronous; and a low level at the clear inputs sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to all low outputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs may occur, regardless of the logic level of the clock. These counters feature a fully independent clock circuit. Changes made to control inputs (enable P or T or load) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable set-up and hold times.
Features
n n n n n n n n n Synchronously programmable Internal look-ahead for fast counting Carry output for n-bit cascading Synchronous counting Load control line Diode-clamped inputs Typical propagation time, clock to Q output 14 ns Typical clock frequency 32 MHz Typical power dissipation 93 mW
Connection Diagram
Dual-In-Line Package
DS006397-1
Order Numbers 54LS161ADMQB, 54LS161AFMQB, 54LS161ALMQB, 54LS163ADMQB, 54LS163AFMQB, 54LS163ALMQB, DM54LS161AJ, DM54LS161AW, DM54LS163AJ, DM54LS163AW, DM74LS161AM, DM74LS161AN, DM74LS163AM or DM74LS163AN See Package Number E20A, J16A, M16A, N16E or W16A
(c) 1998 Fairchild Semiconductor Corporation
DS006397
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Absolute Maximum Ratings (Note 1)
Supply Voltage Input Voltage Operating Free Air Temperature Range 7V 7V
DM54LS and 54LS DM74LS Storage Temperature Range
-55C to +125C 0C to +70C -65C to +150C
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK tW Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 2) Clock Frequency (Note 3) Pulse Width (Note 2) Pulse Width (Note 3) tSU Setup Time (Note 2) Setup Time (Note 3) tH Hold Time (Note 2) Hold Time (Note 3) tREL TA Clock Clear Clock Clear Data Enable P Load Data Enable P Load Data Others Data Others 0 0 20 20 25 25 20 25 25 20 30 30 0 0 5 5 20 25 -55 125 -3 -3 8 17 15 6 9 Parameter Min 4.5 2 0.7 -0.4 4 25 20 0 0 20 20 25 25 20 25 25 20 30 30 0 0 5 5 20 25 0 70 ns ns C -3 -3 ns ns ns 8 17 15 ns 6 9 ns DM54LS161A Nom 5 Max 5.5 Min 4.75 2 0.8 -0.4 8 25 20 DM74LS161A Nom 5 Max 5.25 V V V mA mA MHz MHz ns Units
Clear Release Time (Note 2) Clear Release Time (Note 3) Free Air Operating Temperature
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the "Electrical Characteristics" table are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: CL = 15 pF, RL = 2 k, TA = 25C and VCC = 5.5V. Note 3: CL = 50 pF, RL = 2 k, TA = 25C and VCC = 5.5V.
'LS161 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Conditions VCC = Min, II = -18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min Min Typ (Note 4) -1.5 DM54 DM74 DM54 DM74 DM74 2.5 2.7 3.4 3.4 0.25 0.35 0.25 0.4 0.5 0.4 V V V Max Units
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'LS161 Electrical Characteristics
Symbol II Parameter Input Current @ Max Input Voltage VCC = Max VI = 7V
(Continued)
over recommended operating free air temperature range (unless otherwise noted) Conditions Enable T Clock Load Others IIH High Level Input Current VCC = Max VI = 2.7V Enable T Clock Load Others IIL Low Level Input Current VCC = Max VI = 0.4V Enable T Clock Load Others IOS ICCH ICCL Short Circuit Output Current Supply Current with Outputs High Supply Current with Outputs Low
Note 4: All typicals are at VCC = 5V, TA = 25C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 6: ICCH is measured with the load high, then again with the load low, with all other inputs high and all outputs open. Note 7: ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open.
Min
Typ (Note 4)
Max 0.2 0.2 0.2 0.1 40 40 40 20 -0.8 -0.8 -0.8 -0.4
Units
mA
A
mA
VCC = Max (Note 5) VCC = Max (Note 6) VCC = Max (Note 7)
DM54 DM74
-20 -20 18 19
-100 -100 31 32
mA mA mA
'LS161 Switching Characteristics
at VCC = 5V and TA = 25C From (Input) Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time High to Low Level Output Clock to Ripple Carry Clock to Ripple Carry Clock to Any Q (Load High) Clock to Any Q (Load High) Clock to Any Q (Load Low) Clock to Any Q (Load Low) Enable T to Ripple Carry Enable T to Ripple Carry Clear to Any Q 28 45 ns 15 27 ns 14 27 ns 27 38 ns 24 30 ns 27 38 ns 22 27 ns 30 38 ns To (Output) CL = 15 pF Min 25 25 Max RL = 2 k CL = 50 pF Min 20 30 Max MHz ns Units
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Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK tW Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 8) Clock Frequency (Note 9) Pulse Width (Note 8) Pulse Width (Note 9) tSU Setup Time (Note 8) Setup Time (Note 9) tH Hold Time (Note 8) Hold Time (Note 9) tREL TA Clock Clear Clock Clear Data Enable P Load Data Enable P Load Data Others Data Others 0 0 20 20 25 25 20 25 25 20 30 30 0 0 5 5 20 25 -55 125 -3 -3 8 17 15 6 9 Parameter Min 4.5 2 0.7 -0.4 4 25 20 0 0 20 20 25 25 20 25 25 20 30 30 0 0 5 5 20 25 0 70 ns ns C -3 -3 ns ns ns 8 17 15 ns 6 9 ns DM54LS163A Nom 5 Max 5.5 Min 4.75 2 0.8 -0.4 8 25 20 DM74LS163A Nom 5 Max 5.25 V V V mA mA MHz MHz ns Units
Clear Release Time (Note 8) Clear Release Time (Note 9) Free Air Operating Temperature
Note 8: CL = 15 pF, RL = 2 k, TA = 25C and VCC = 5V. Note 9: CL = 50 pF, RL = 2 k, TA = 25C and VCC = 5V.
'LS163 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage II Input Current @ Max Input Voltage Conditions VCC = Min, II = -18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max VI = 7V Min Typ (Note 10) -1.5 DM54 DM74 DM54 DM74 DM74 Enable T Clock, Clear Load Others IIH High Level Input Current VCC = Max VI = 2.7V Enable T Load Clock, Clear Others 2.5 2.7 3.4 3.4 0.25 0.35 0.25 0.4 0.5 0.4 0.2 0.2 0.2 0.1 40 40 40 20 A mA V V V Max Units
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'LS163 Electrical Characteristics
Symbol IIL Parameter Low Level Input Current VCC = Max VI = 0.4V
(Continued)
over recommended operating free air temperature range (unless otherwise noted) Conditions Enable T Clock, Clear Load Others IOS ICCH ICCL Short Circuit Output Current Supply Current with Outputs High Supply Current with Outputs Low VCC = Max (Note 11) VCC = Max (Note 12) VCC = Max (Note 13) DM54 DM74 -20 -20 18 18 Min Typ (Note 10) -0.8 -0.8 -0.8 -0.4 -100 -100 31 32 mA mA mA mA Max Units
Note 10: All typicals are at VCC = 5V, TA = 25C. Note 11: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 12: ICCH is measured with the load high, then again with the load low, with all other inputs high and all outputs open. Note 13: ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open.
'LS163 Switching Characteristics
at VCC = 5V and TA = 25C From (Input) Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time High to Low Level Output Clock to Ripple Carry Clock to Ripple Carry Clock to Any Q (Load High) Clock to Any Q (Load High) Clock to Any Q (Load Low) Clock to Any Q (Load Low) Enable T to Ripple Carry Enable T to Ripple Carry Clear to Any Q (Note 14) 28 45 ns 15 27 ns 14 27 ns 27 38 ns 24 30 ns 27 38 ns 22 27 ns 30 38 ns To (Output) CL = 15 pF Min 25 25 Max RL = 2 k CL = 50 pF Min 20 30 Max MHz ns Units
Note 14: The propagation delay clear to output is measured from the clock input transition.
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Logic Diagram
LS163A
DS006397-2
The LS161A is similar, however, the clear buffer is connected directly to the flip flops.
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Parameter Measurement Information
Switching Time Waveforms
DS006397-3
Note 15: The input pulses are supplied by generators having the following characteristics: PRR 1 MHz, duty cycle 50%, ZOUT 50, tr 10 ns, tf 10 ns. Vary PRR to measure fMAX. Note 16: Outputs QD and carry are tested at tn+16 where tn is the bit time when all outputs are low. Note 17: VREF = 1.5V.
Switching Time Waveforms
DS006397-4
Note 18: The input pulses are supplied by generators having the following characteristics: PRR 1 MHz, duty cycle 50%, ZOUT 50, tr 6 ns, tf 6 ns. Vary PRR to measure fMAX. Note 19: Enable P and enable T setup times are measured at tn+0. Note 20: VREF = 1.3V.
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Timing Diagram
LS161A, LS163A Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences
DS006397-5
Sequence: (1) Clear outputs to zero (2) Preset to binary twelve (3) Count to thirteen, fourteen, fifteen, zero, one, and two (4) Inhibit
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Physical Dimensions
inches (millimeters) unless otherwise noted
Ceramic Leadless Chip Carrier Package (E) Order Numbers 54LS161ALMQB or 54LS163ALMQB Package Number E20A
16-Lead Ceramic Dual-In-Line Package (J) Order Numbers 54LS161ADMQB, 54LS163ADMQB, DM54LS161AJ or DM54LS163AJ Package Number J16A
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Molded Package (M) Order Number DM74LS161AM or DM74LS163AM Package Number M16A
16-Lead Molded Dual-In-Line Package (N) Order Numbers DM74LS161AN, DM74LS163AN Package Number N16E
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DM74LS161A/DM74LS163A Synchronous 4-Bit Binary Counters
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Ceramic Flat Package (W) Order Numbers 54LS161AFMQB, 54LS163AFMQB, DM54LS161AN or DM54LS163AW Package Number W16A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and (c) whose device or system, or to affect its safety or effectiveness. failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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